The present invention relates to a semiconductor memory device and a method of fabricating the same, and more particularly, to a static random access memory (hereinafter referred to as SRAM) cell and method of fabricating the same.
Generally, an SRAM cell consists of either four transistors (for example, two for accessing and two for driving) and two polysilicon load resistors, or six transistors. A high density memory cell of over 4Mb is made in the form of CMOS transistors, consisting of four NMOS transistors and two PMOS transistors.
FIG. 1 is an equivalent circuit of a conventional CMOS-type SRAM. Referring to this drawing, four NMOS transistors Q1-Q4 are formed on a semiconductor substrate. Two PMOS transistors Q5 and Q6 are formed thereon as thin film transistors (TFTs).
A method of fabricating the conventional SRAM of FIG. 1 will be discussed below with reference to FIGS. 2A-5.
FIG. 2a is a layout of bulk transistors of an SRAM cell in accordance with the conventional art.
FIG. 2b is a layout of TFTs of the SRAM cell in accordance with the conventional art.
FIG. 3 is a layout of an SRAM cell constructed in such a manner that the TFTs of FIG. 2b are formed on the bulk transistors of FIG. 2a.
FIG. 4 is a cross-sectional view of the SRAM cell shown in FIG. 3, taken along the line IV--IV of FIG. 3.
FIG. 5 is a cross-sectional view of the SRAM cell of FIG. 3, taken along the line V--V of FIG. 3.
Referring to FIGS. 2a-5, according to the method of fabricating the conventional SRAM cell, active regions 32 and field regions 32a are defined on a semiconductor substrate 31.
A first gate oxide 33 is formed on the active regions 32. Polysilicon and cap gate nitride 34 are sequentially deposited on the first gate oxide 33. They are patterned and etched through photolithography to define a first gate electrode 35. A sidewall oxide 37 is formed on both sides of the first gate electrode 35.
Subsequently, first and second impurity-doped regions 39 and 41 are formed by ion-implanting polysilicon into the active regions 32. A first interlevel insulating layer 43 is then deposited on the overall surface of the substrate, and selectively etched to expose a predetermined portion thereof. Polysilicon is deposited on the first interlevel insulating layer 43 and contacts the first impurity-doped region 39, to form a Vss line 44.
A second interlevel insulating layer 45 and polysilicon are deposited on the Vss line 44 having a contact 44a. The obtained polysilicon layer is patterned through photolithography, to form a second gate electrode 46 having a contact 46a. A second gate oxide 47 and polysilicon are deposited on the overall surface of the substrate. Using an offset mask 48, impurities are doped into the second gate oxide 47 to form a body 49 of a TFT. The formed TFT comprises source, drain and channel regions. Then, to improve the characteristics of the transistor, heat treatment is carried out. As a result, the grain size of the polysilicon in the body 49 is enlarged. The conventional SRAM cell further includes an insulating layer 50 and a bitline 51 having a contact 51a.
After performing exposure and etch processes, a metallization process is performed to finish forming the SRAM cell. However, the SRAM cell formed by the conventional method involves several problems.
First, when the TFT is formed on the bulk transistor, the process of forming the second gate electrode is carried out independent of that of the first gate electrode. This increases the number of processing steps necessary in forming a TFT.
Second, accurate offset alignment is difficult to achieve because the position of the offset mask of the TFTs varies with the arrangement of the bulk transistor. This deteriorates the characteristics of the TFTs.
Third, the second gate electrode and body of the TFTs are formed on the bulk transistor, resulting in poor step coverage. As a result, it becomes difficult to perform the metallization process.